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X55060
64K
Data Sheet March 28, 2005 FN8133.0
PRELIMINARY
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FEATURES * Dual voltage monitoring * Active high and active low reset outputs * Four standard reset threshold voltages (4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6) --User programmable thresholds * Lowline Output -- Zero delayed POR * Reset signal valid to VCC = 1V * System battery switch-over circuitry * Long battery life with low power consumption --<50A max standby current, watchdog on --<30A max standby current, watchdog off * Selectable watchdog timer --(0.15s, 0.4s, 0.8s, off) * 64Kbits of EEPROM * Built-in inadvertent write protection --Power-up/power-down protection circuitry --Protect none(0), or all of EEPROM array with programmable Block LockTM protection BLOCK DIAGRAM
--In circuit programmable ROM mode * Minimize EEPROM programming time --64 byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * 10MHz SPI interface modes (0,0 & 1,1) * 2.7V to 5.5V power supply operation * Available packages -- 20-lead TSSOP DESCRIPTION This device combines power-on reset control, battery switch circuit, watchdog timer, supply voltage supervision, secondary voltage supervision, block lock protect and serial EEPROM in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code.
VOUT V2MON V2 Monitor Logic
+
V2FAIL
VTRIP2
-
Watchdog Transition Detector WP SO SI Data Register Command Decode, Test & Control Logic Protect Logic Status Register EEPROM Array
Watchdog Timer Reset
WDO
RESET
X-Decoder
Reset & Watchdog Timebase BATT-ON
SCK CS
512 X 128
VOUT VBATT VCC
(V1MON)
System Battery Switch VCC Monitor Logic
+ VTRIP1 -
RESET/MR VOUT Power-on, Low Voltage Reset Generation LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X55060
A system battery switch circuit compares VCC (V1MON) with VBATT input and connects VOUT to whichever is higher. This provides voltage to external SRAM or other circuits in the event of main power failure. The X55060 can drive 50mA from VCC and 250A from VBATT. The device switches to VBATT when VCC drops below the low VCC voltage threshold and VBATT > VCC. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the WDO signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC (V1MON) falls below the minimum VCC trip point (VTRIP1). RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. A second voltage monitor circuit tracks the unregulated PIN CONFIGURATION
20-Pin TSSOP CS/WDI NC SO RESET LOWLINE V2FAIL V2MON WP NC VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC (V1MON) WDO RESET/MR BATT-ON VOUT VBATT SCK NC NC SI
supply or monitors a second power supply voltage to provide a power fail warning. Intersil's unique circuits allow the threshold for either voltage monitor to be reprogrammed to meet special needs or to fine-tune the threshold for applications requiring higher precision. ORDERING INFORMATION X55060 Suffix
V20-4.5A V20I-4.5A V20-4.5 V20I-4.5 V20-2.7A V20I-2.7A V20-2.7 V20I-2.7
Vtrip1
4.6 4.6 2.9 2.6
Vtrip2
2.6 2.9 1.65 1.65
Temp Range
0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
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PIN DESCRIPTION Pin
1
Name
CS/WDI
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. No internal connections Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Reset Output. RESET is an active HIGH, open drain output which is the inverse of the RESET output. Low VCC Detect. This open drain output signal goes LOW when VCC < VTRIP1 and immediately goes HIGH when VCC > VTRIP1. This pin goes LOW 250ns before RESET pin. V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the Watchdog Timer control and the memory write protect bits. No internal connections Ground Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. No internal connections No internal connections Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Battery Supply Voltage. This input provides a backup supply in the event of a failure of the primary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to maintain the contents of SRAM and also powers the internal logic to "stay awake." If unused connect VBATT to ground.
2 3 4 5 6
NC SO RESET LOWLINE V2FAIL
7
V2MON
8 9 10 11
WP NC VSS SI
12 13 14
NC NC SCK
15
VBATT
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PIN DESCRIPTION (CONTINUED) Pin
16
Name
VOUT
Function
Output Voltage. VOUT = VCC if VCC > VTRIP1. IF VCC < VTRIP1, then, VOUT = VCC if VCC > VBATT+0.03 VOUT = VBATT if VCC < VBATT-0.03 Note: There is hysteresis around VBATT 0.03V point to avoid oscillation at or near the switchover voltage. A capacitance of 0.1F must be connected to Vout to ensure stability. Battery On. This open drain output goes HIGH when the VOUT switches to VBATT and goes LOW when VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current requirements are greater than 50mA. The purpose of this output is to drive an external transistor to get higher operating currents when the VCC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT pin and the external transistor is turned off. In this "backup condition," the battery only needs to supply enough voltage and current to keep SRAM devices from losing their data-there is no communication at this time. Output/Manual Reset Input. This is an Input/Output pin. RESET Output. This is an active LOW, open drain output which goes active whenever VCC falls below the minimum VCC sense level. When RESET is active communication to the device is interrupted. RESET remains active until VCC rises above the minimum VCC sense level for 150ms. RESET also goes active on power-up and remains active for 150ms after the power supply stabilizes. MR Input. This is an active LOW debounced input. When MR is active, the RESET/RESET pins are asserted. When MR is released, the RESET/RESET remains asserted for tPURST, and then released. Watchdog Output. WDO is an active low, open drain output which goes active whenever the watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state. Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1 voltage, RESET and RESET go ACTIVE.
17
BATT-ON
18
RESET /MR
19 20
WDO VCC (V1MON)
PRINCIPLES OF OPERATION Power-On Reset Application of power to the X55060 activates a Poweron Reset Circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP1 value for 150ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low VCC (V1MON) Voltage Monitoring During operation, the X55060 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP1. During this time the communication to the device is interrupted. The
RESET/RESET signal also prevents the microprocessor from operating in a power fail or brownout condition. The RESET signal remains active until the voltage drops below 1V. These also remain active until VCC returns and exceeds VTRIP1 for tPURST. Low V2MON Voltage Monitoring The X55060 also monitors a second voltage level and asserts V2FAIL if the voltage falls below a preset minimum VTRIP2. The V2FAIL signal is either ORed with RESET to prevent the microprocessor from operating in a power fail or brownout condition or used to interrupt the microprocessor with notification of an impending power failure. V2FAIL remains active until V2MON returns and exceeds VTRIP2. The V2MON voltage sensor is powered by VOUT. If VCC and VBATT go away (i.e. VOUT goes away), then V2MON cannot be monitored.
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Figure 1. Two Uses of Dual Voltage Monitoring
X55060 Unregulated Supply R1 R2 V2 5V Reg VCC RESET V2MON V2FAIL VOUT X55060 System Reset System Interrupt Unregulated Supply 5V Reg VCC VOUT
RESET System Reset
3.3V Reg
V2MON V2FAIL
R1 and R2 selected so V2 = V2MON threshold when Unregulated supply reaches 6V.
Notice: No external components required to monitor two voltages.
Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the CS/WDI pin. The microprocessor must toggle the CS/WDI pin HIGH to LOW periodically prior to the expiration of the watchdog time out period to prevent the WDO signal going active. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits by writing to the status register. The factory default setting disables the watchdog timer. The Watchdog Timer oscillator stops when in battery backup mode. It re-starts when VCC returns. System Battery Switch As long as VCC exceeds the low voltage detect threshold VTRIP1, VOUT is connected to VCC through a 5 (typical) switch. When the VCC has fallen below VTRIP, then VCC is applied to VOUT if VCC is equal to or greater than VBATT + 0.03V. When VCC drops to less than VBATT - 0.03V, then VOUT is connected to VBATT through an 80 (typical) switch. VOUT typically supplies the system static RAM voltage, so the switchover circuit operates to protect the contents of the static RAM during a power failure. Typically, when VCC has failed, the SRAMs go into a lower power state and draw much less current than in their active mode. When VCC returns, VOUT switches back to VCC when VCC exceeds VBATT + 0.03V. There is a 60mV hysteresis around this battery switch threshold to prevent oscillations between supplies.
While VCC is connected to VOUT the BATT-ON pin is pulled LOW. The signal can drive an external PNP transistor to provide additional current to the external circuits during normal operation. Operation The device is in normal operation with VCC as long as VCC > VTRIP1. It switches to the battery backup mode when VCC goes away. Condition
VCC > VTRIP1 VCC > VTRIP1 & VBATT = 0 0 VCC VTRIP1 and VCC < VBATT
Mode of Operation
Normal Operation. Normal Operation without battery back up capability. Battery Backup Mode; RESET signal is asserted. No communication to the device is allowed.
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Manual Reset By connecting a push-button from MR to ground or driven by logic, the designer adds manual system reset capability. The RESET/RESET pins are asserted when the push-button is closed and remain asserted for tPURST after the push-button is released. This pin is debounced so a push-button connected directly to the device will have both clean falling and rising edges on MR. VCC (V1MON), V2MON Threshold Programming Procedure The X55060 is shipped with standard VCC (V1MON) and V2MON threshold (VTRIP1, VTRIP2) voltages. These values will not change over normal operating and storage conditions. However, in applications where the standard thresholds are not exactly right, or if higher precision is needed in the threshold value, the X55060 trip points may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP1 or VTRIP2 to a lower or higher voltage value. It is necessary to reset the trip point before setting the new value to a lower level. To set the new voltage, apply the desired VTRIP1 threshold voltage to the VCC pin or the VTRIP2 voltage to the V2MON pin (when setting VTRIP2, VCC should be same voltage as V2MON). Next, tie the WP pin to Figure 2. Example System Connection
Unregulated Supply 5V Reg VCC PNP transistor or P-channel FET
the programming voltage VP. Then, send the WREN command and write to address 01h or to address 0Bh to program VTRIP1 or VTRIP2, respectively (followed by data byte 00h). The CS going high after a valid write operation initiates the programming sequence. Bring WP LOW to complete the operation. To check if the VTRIPX has been set, apply a voltage higher than VTRIPX to the VXMON (x = 1, 2) pin. Decrement VXMON in small steps and observe where the output switches. The voltage at which this occurs is the VTRIPX (actual). CASE A If the VTRIPX (actual) is lower than the VTRIPX (desired), then add the difference between VTRIPX (desired) and VTRIPX (actual) to the original VTRIPX (desired). This is your new VTRIPX voltage that should be applied to VXMON and the whole sequence repeated again (see Fig 6). CASE B If the VTRIPX (actual) is higher than the VTRIPX (desired), perform the reset sequence as described in the next section. The new VTRIPX voltage to be applied to VXMON will now be: VTRIPX (desired) - (VTRIPX (desired) - VTRIPX (actual)). Note: This operation will not alter the contents of the EEPROM.
BATT-ON VOUT VOUT Address Decode V2FAIL Enable
SRAM
VBATT V2MON +
NMI RESET CS, SCK SI, SO
Addr VCC
RESET SPI C
VSS
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Resetting the VTRIP Voltage To reset VTRIP1, apply greater than 3V to VCC (V1MON). To reset VTRIP2, apply greater than 3V to both VCC and V2MON. Next, tie the WP pin to the programming voltage VP. Then send the WREN command and write to address 03h or 0Dh to reset the VTRIP1 or VTRIP2 respectively (followed by data byte Figure 3. Set VTRIPX Level Sequence
WP VP = 10-15V
00h). The CS going LOW to HIGH after a valid write operation initiates the programming sequence. Bring WP LOW to complete the operation. Note: This operation does not change the contents of the EEPROM array.
CS 01234567 SCK 16 Bits SI 06h WREN 02h WRITE 0001h/000Bh ADDRESS Addr 01h: Set VTRIP1 Addr 0Bh: Set VTRIP2 00h DATA 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
Figure 4. Reset VTRIPX Level Sequence
WP VP = 10-15V
CS 01234567 SCK 16 Bits SI 06h WREN 02h WRITE 0003h/000Dh ADDRESS Addr 03h: Reset VTRIP1 Addr 0Dh: Reset VTRIP2 00h DATA 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
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Figure 5. Sample VTRIP Circuit
4.7K VP Adjust VTRIP Adj. X55060 VCC CS RESET SO SCK WP VSS SI RESET SCK SI SO CS C
Run
Figure 6. VTRIP Programming Sequence Flow Chart
VTRIPX Programming Vx = VxMON Note: X = 1, 2 Let: MDE = Maximum Desired Error
No
Desired VTRIPX < Present Value? YES Execute VTRIPX Reset Sequence
MDE+ Acceptable Desired Value Error Range MDE- Error = Actual - Desired
Set VX = desired VTRIPX
New VX applied = Old VX applied + | Error |
Execute Set Higher VTRIPX Sequence
New VX applied = Old VX applied - | Error |
Apply VCC and Voltage > Desired VTRIPX to VX NO Decrease VX
Execute Reset VTRIPX Sequence
Output Switches? YES Error < MDE- Actual VTRIPX Desired VTRIPX | Error | < | MDE | DONE Error > MDE+
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SPI SERIAL MEMORY The memory portion of the device is a CMOS Serial EEPROM array with Intersil's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Table 1. Instruction Set Instruction Name
WREN WRDI RSDR WRSR READ WRITE
Note:
Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction sets the latch and the WRDI instruction resets the latch (Figure 9). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. Status Register The RDSR instruction provides access to the Status Register. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows: 7
WPEN
6
5
4
3
BL1
2
BL0
1
0
WD1 WD0 PUP
WEL WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress.
Instruction Format*
0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Reset the Write Enable Latch Read Status Register
Operation
Set the Write Enable Latch (Enable Write Operations)
Write Status Register (Watchdog, block lock, WPEN) Read Data from Memory Array Beginning at Selected Address Write Data to Memory Array Beginning at Selected Address
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix WREN CMD WEL
0 1 1 1
Status Register WPEN
X 1 0 X
Device Pin WP
X 0 X 1
Block Protected Block
Protected Protected Protected Protected
Block Unprotected Block
Protected Writable Writable Writable
Status Register WPEN, BL0, BL1, PUP, WD0, WD1
Protected Protected Writable Writable
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The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. Status Register Bits BL1
0 0 1 1
The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. Status Register Bits WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time Out (Typical)
800 milliseconds 400 milliseconds 150 milliseconds disabled (factory setting)
Array Addresses Protected X55060
None (factory setting) None None 0000h-1FFFh (All)
BL0
0 1 0 1
The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide an In-Circuit Programmable ROM function (Table 2). WP tied to VSS and WPEN bit programmed HIGH disables all Status Register Write Operations. Note 1. Watchdog timer is shipped disabled. 2. The tPURST time is set to 150ms at the factory. In Circuit Programmable ROM Mode This mechanism protects the block lock and Watchdog bits from inadvertent corruption. In the locked state (Programmable ROM Mode) the WP pin is LOW and the nonvolatile bit WPEN is "1". This mode disables nonvolatile writes to the device's Status Register. Setting the WP pin LOW while WPEN is a "1" while an internal write cycle to the Status Register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the Status Register.
The power-on reset time (tPURST) bit, PUP sets the initial power or reset time. There are two standard settings. PUP
0 1
Time
150 milliseconds (factory settings) 800 milliseconds
Figure 7. Read EEPROM Array Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
Instruction SI
16 Bit Address 15 14 13 3 2 1 0
Data Out High Impedance SO 7 MSB 6 5 4 3 2 1 0
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When WP is HIGH, all functions, including nonvolatile writes to the Status Register operate normally. Setting the WPEN bit in the Status Register to "0" blocks the WP pin function, allowing writes to the Status Register when WP is HIGH or LOW. Setting the WPEN bit to "1" while the WP pin is LOW activates the Programmable ROM mode, thus requiring a change in the WP pin prior to subsequent Status Register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the Status Register. Manufacturing can then load Configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the "OTP mode" by setting the WPEN bit. Data changes to protected areas of the device now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. The read operation is terminated by taking CS high. Refer to the Read EEPROM Array Sequence (Figure 7). To read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 8). Refer to the Serial Output Timing on page 18. Write Sequence Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 9). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 10). To write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 11). While the write is in progress following a Status Register or EEPROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high. Refer to Serial Input timing on page 17. OPERATIONAL NOTES The device powers-up in the following state: - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. - SO pin is high impedance. - The Write Enable Latch is reset. - Reset Signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: - A WREN instruction must be issued to set the Write Enable Latch. - A valid write command and address must be sent to the device. - CS must come HIGH after a multiple of 8 data bits in order to start a nonvolatile write cycle.
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Figure 8. Read Status Register Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
Instruction SI
Data Out SO High Impedance 7 MSB 6 5 4 3 2 1 0
Figure 9. Write Enable Latch Sequence
CS
0 SCK
1
2
3
4
5
6
7
SI
SO
High Impedance
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Figure 10. Write Sequence
CS 0 SCK Instruction SI 16 Bit Address 15 14 13 3 2 1 0 7 6 5 Data Byte 1 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 5 Data Byte 3 4 3 2 1 0 6 5 Data Byte N 4 3 2 1 0
Figure 11. Status Register Write Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 7 6 5
Data Byte 4 3 2 1 0
SO
High Impedance
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65C to +135C Storage temperature ........................ -65C to +150C Voltage on any pin with respect to VSS ...................................... -1.0V to +7V D.C. output current (all output pins except VOUT)............................. 5mA D.C. Output Current VOUT .................................. 50mA Lead temperature (soldering, 10 seconds) ........ 300C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. 70C +85C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified. (VCC = 2.7V to 5.5V)) Limits Symbol
ICC1(1)
Parameter
VCC Supply Current (Active) (Excludes IOUT) Read Memory array (Excludes IOUT) Write nonvolatile Memory VCC Supply Current (Passive) (Excludes IOUT) WDT on, 5V (Excludes IOUT) WDT on, 2.7V (Excludes IOUT) WDT off, 5V VCC Current (Battery Backup Mode) (Excludes IOUT) VBATT Current (Excludes IOUT) VBATT Current (Excludes IOUT) (Battery Backup Mode) Output Voltage (VCC > VBATT + 0.03V or VCC > VTRIP1) Output Voltage (VCC < VBATT -0.03V and VCC < VTRIP1) {Battery Backup} Output (BATT-ON) LOW Voltage Battery Switch Hysteresis (VCC < VTRIP1) VCC Reset Trip Point Voltage
Min.
Typ.(5)
Max.
1.5 3.0
Unit
mA
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 10MHz CS = VCC, Any Input = VSS or VCC, VOUT, RESET, RESET, LOWLINE = Open VCC = 2V, VBATT = 2.8V, VOUT, RESET = Open VOUT = VBt VOUT = VBATT, VBATT = 2.8V VOUT, RESET = Open IOUT = -5mA IOUT = -50mA IOUT = -250A IOL = 3.0mA (5V) IOL = 1.0mA (3V) Power-up Power-down -4.5A and -4.5 versions -2.7A version -2.7 version IOL = 3.0mA (5V) IOL = 1.0mA (3V)
FN8133.0 March 28, 2005
ICC2(2)
A 50.0 40.0 30.0 90.0 60.0 50.0 1 A
ICC3(1)
IBATT1(3)(7
)
1 0.4 1.0
A A
IBATT2(7)
VOUT1(7) VOUT2(7) VOLB VBSH
VCC - 0.05 VCC - 0.5 VBATT - 0.2
VCC-0.02 VCC-0.2
V V V V
0.4 30 -30 4.5 2.85 2.55 4.62 4.75 3.0 2.75 0.4
V mV mV V V V V
RESET/RESET/LOWLINE/WDO
VTRIP1(6)
VOLR
Output (RESET, RESET, LOWLINE, WDO) LOW Voltage
14
X55060
D.C. OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions unless otherwise specified. (VCC = 2.7V to 5.5V)) Limits Symbol Second Supply Monitor
VTRIP2(6) V2MON Reset Trip Point Voltage 2.85 2.55 1.6 VOLx Output (V2FAIL) LOW Voltage 3.0 2.7 1.7 0.4 V V V V -4.5 version -4.5A version -2.7A and -2.7 version IOL = 3.0mA (5V) IOL = 1.0mA (3V)
Parameter
Min.
Typ.(5)
Max.
Unit
Test Conditions
SPI Interface
VILx(4) VIHx
(4)
Input (CS, SI, SCK, WP) LOW Voltage Input (CS, SI, SCK, WP) HIGH Voltage Input Leakage Current (CS, SI, SCK,WP) Output (SO) LOW Voltage Output (SO) HIGH Voltage
-0.5 VCC x 0.7
VCC x 0.3 VCC + 0.5 10 0.4
V V A V V IOL = 3.0mA (5V) IOL = 1.0mA (3V) IOH = -1.0mA (5V)
ILIx VOLS VOHS
VOUT - 0.8
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) Negative number indicate charging current, Positive numbers indicate discharge current. (4) VIL min. and VIH max. are for reference only and are not tested. (5) VCC = 5V at 25C. (6) VTRIP1 and VTRIP2 are programmable. See page 22 and 23 for programming specifications and pages 6, 7 and 8 for programming procedure. For custom programmed levels, contact factory. (7) Based on characterization data.
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol COUT(1)
CIN(1)
Note:
Test Output Capacitance (SO, RESET, V2FAIL, RESET, LOWLINE, BATT-ON,WDO)
Input Capacitance (SCK, SI, CS, WP)
Max. 8
6
Unit pF
pF
Conditions VOUT = 0V
VIN = 0V
(1) This parameter is periodically sampled and not 100% tested.
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FN8133.0 March 28, 2005
X55060
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
VOUT VOUT 1.53k RESET/RESET BATT-ON/LOWLINE/ V2FAIL, WDO 30pF 30pF
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
2.06k SO 3.03k
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing VCC = 2.7-5.5V Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI
(3)
Parameter
Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Input Rise Time Input Fall Time CS Deselect Time Write Cycle Time
Min.
100 50 200 40 40 10 10
Max.
10
Unit
MHz ns ns ns ns ns ns ns
20 20 50 10
ns ns ns ms
tCS tWC
(4)
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FN8133.0 March 28, 2005
X55060
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
High Impedance SO
Serial Output Timing 2.7-5.5V Symbol
fSCK tDIS tV tHO tRO tFO
(3) (3)
Parameter
Clock Frequency Output Disable Time Output Valid from Clock Low Output Hold Time Output Rise Time Output Fall Time
Min.
Max.
10 50 40
Unit
MHz ns ns ns ns ns
0 25 25
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
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FN8133.0 March 28, 2005
X55060
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
Power-Up and Power-Down Timing
VTRIP1 VCC 0V tRPD
VBATT
tPURST RESET
tPURST
VCC VBAT VOUT 0V
RESET tVB1 tVB2
VOUT
VOUT BATT-ON
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FN8133.0 March 28, 2005
X55060
VCC to LOWLINE Timings
VCC VTRIP1 tRPD 0V VOH LOWLINE VOL VTRIP1 VBATT 0V tR tRPD tF VTRIP
V2MON to V2FAIL Timings
VTRIP2 0V tR V2FAIL tRPD2 tRPD2 tF VOUT
V2MON
RESET/RESET/LOWLINE Output Timing Symbol
tPURST
Parameter
RESET/RESET Time-out Period PUP = 0 PUP = 1 VTRIP1 to RESET/RESET (Power-down only) VTRIP1 to LOWLINE VTRIP2 to V2FAIL LOWLINE to RESET/RESET delay (Power-down only) VCC/V2MON Fall Time VCC/V2MON Rise Time Reset Valid VCC VBATT + 0.03 v to BATT-ON (logical 0) VBATT - 0.03 v to BATT-ON (logical 1)
Min.
75 500
Typ.(3)
150 800 10 10
Max.
250 1200 20 20 800
Unit
ms s s ns s s V
tRPD(1) tRPD2(1) tLR tF(2) tR
(2)
100 1000 1000 1
250(4)
VRVALID tVB1 tVB2
Notes: (1) (2) (3) (4)
20(4) 20(4)
s s
This parameter is not 100% tested. This measurement is from 10% to 90% of the supply voltage. VCC = 5V at 25C. Based on characterization data only.
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FN8133.0 March 28, 2005
X55060
CS/WDI vs. WDO Timing
CS/WDI tCST WDO tWDO tRST tWDO tRST
RESET/RESET Output Timing Symbol
tWDO
Parameter
Watchdog Time Out Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS Pulse Width to Reset the Watchdog Reset Time Out
Min.
75 200 500 400 75
Typ.(1)
150 400(2) 800(2) 150
Max.
250 600 1200 250
Unit
ms ms ms ns ms
tCST tRST
Notes: (1) VCC = 5V at 25C. (2) Based on characterization data only.
VTRIP Set/Reset Conditions
VCC/V2MON tTSU VP WP tVPS CS
8 clocks
VTRIPX
tTHD
tPCS
tVPH tVPO tWC
SCK
SI 06h X = 1, 2 02h
0n * 0001h Set VTRIP1 * 0003h Set VTRIP2 * 000Bh Reset VTRIP1 * 000Dh Reset VTRIP2 * all others reserved
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FN8133.0 March 28, 2005
X55060
VTRIP1, VTRIP2 Programming Specifications VCC = 2.7-5.5V; Temperature = 25C Parameter
tVPS tVPH tTSU tTHD tWC tVPO VP VTRAN Vtv
Description
WP VTRIPX Program Voltage Setup time WP VTRIPX Program Voltage Hold time VTRIPX Level Setup time VTRIPX Level Hold (stable) time VTRIPX Write Cycle Time WP VTRIPX Program Voltage Off time before next cycle Programming Voltage VTRIPX Programed Voltage Range VTRIPX Program variation after programming (0-75C). (Programmed at 25C according to the procedure defined on pages 6, 7 and 8.)
Min. Max.
10 10 10 10 10 1 10 2.5 -25 15 5.0 +25
Unit
s s s ms ms ms V V mV
VTRIPX programming parameters are periodically sampled and are not 100% tested.
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FN8133.0 March 28, 2005
X55060
PACKAGING INFORMATION 20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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FN8133.0 March 28, 2005
X55060
Part Mark Information X55060 YYww W X V20 = 20-Lead TSSOP
Date Code
Part Mark
Blank I AL AM F G AN AP
VTRIP1 Range
4.5-4.75V 4.5-4.75V 2.85-3.0V 2.55-2.75V
VTRIP2 Range
2.55-2.7V 2.85-3.0V 1.6-1.7V 1.6-1.7V
Operating Temperature Range
0C-70C -40C-85C 0C-70C -40C-85C 0C-70C -40C-85C 0C-70C -40C-85C
Part Number
X55060V20-4.5A X55060V20I-4.5A X55060V20-4.5 X55060V20I-4.5 X55060V20-2.7A X55060V20I-2.7A X55060V20-2.7 X55060V20I-2.7
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 23
FN8133.0 March 28, 2005

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